A*STAR researchers have developed a computer model that predicts how a silicon wafer deforms when computer chips are crowded together too closely. The model enables the researchers to study a wide range of factors that influence the warpage of an eight-inch-diameter silicon wafer.
The researchers focused on how a silicon substrate responds to the deposition of layers of copper. "This is the first time that a model has been...able to predict warpage [at] the level of the entire wafer," says A*STAR's Hongyu Li.
The computer simulations also enable the researchers to examine regimes that cannot be easily studied experimentally, such as how the depth of the connections between layers influences wafer warpage.
In the future, the researchers hope to simulate even larger wafers with variable connection sizes, according to Li. "Today, there are two industry standards for 3D packaging applications, 8-inch and 12-inch wafers, but the latter are becoming increasingly important," she notes.
The researchers note their model also applies to these larger wafers, but it needs to be optimized.
From A*STAR Research
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