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Researchers Develop Scaled-up Spintronic Probabilistic Computer


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The research group showed how sMTJ-based p-bits can be combined with conventional and programmable semiconductor chips.

Credit: Tohoku University (Japan)

Scientists at Japan's Tohoku University, Italy's University of Messina, and the University of California, Santa Barbara have engineered a scaled-up probabilistic computer (p-computer) with stochastic spintronic devices.

The researchers demonstrated how stochastic magnetic tunnel junction (sMTJ)-based probabilistic bits (p-bits) can be integrated with field-programmable gate arrays (FPGAs) to implement larger p-bit networks in hardware.

They also executed a simulated quantum annealing algorithm in heterogeneous MTJ + FPGA p-computers with systematic assessments for hard combinatorial optimization problems.

The researchers benchmarked sMTJ-based p-computer performance against that of classical computing hardware, including graphics processing units and Tensor Processing Units, and found it yields superior throughput and power consumption compared to conventional technologies.

From Tohoku University (Japan)
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Abstracts Copyright © 2022 SmithBucklin, Washington, DC, USA


 

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